基于FPGA的嵌入式系统
Single Event Effect Device
- PCB Design (more than 20 board)
- CAD Design
- Software
- Support for the operation of the other modules
Monitor System for SEE
Single-Event-Effect Experiment Environment
- Multi IP Core
- Multi Processor IP Core
- Communication among the Core
- Multi Clocks Control
- Reconfiguration
Design of Multiprocessor Core
System of Single Event Effect
EDAC Encoding
- P0=D7⊕D6⊕D4⊕D3⊕D1
- P1=D7⊕D5⊕D4⊕D2⊕D1
- P2=D5⊕D4⊕D6⊕D0
- P3=D3⊕D2⊕D1⊕D0
- P4=D7⊕D6⊕D5⊕D3⊕D2⊕D0
EDAC Decoding
- S0=P0⊕D7⊕D6⊕D4⊕D3⊕D1
- S1=P1⊕D7⊕D5⊕D4⊕D2⊕D1
- S2=P2⊕D5⊕D4⊕D6⊕D0
- S3=P3⊕D3⊕D2⊕D1⊕D0
- S4=P4⊕D7⊕D6⊕D5⊕D3⊕D2⊕D0
EDAC Algorithm based on FPGA.
- Simulation of Manufacturing System Based on FPGA
- Keyboard Matrix Testing
- Multi-Switch Testing
- Multi-Input Sampling
